1. Field of the Invention
The present invention relates generally to probe cards for testing of semiconductor dice. More specifically, the present invention relates to full-wafer probe cards suitable for use in burn-in and high frequency testing of such semiconductor dice.
2. State of the Art
The front-end process of ultra large-scale integration (ULSI) is often discussed in terms of Moore's law, which states that the number of transistors on a given silicon die will double every 18 to 24 months. Such rapid progress in front-end technology places significant pressure on back-end processes to keep pace. These back-end technologies may include, for example, burn-in, low and high speed testing, as well as dicing and packaging processes to transform the semiconductor dice as fabricated on a wafer or other large-scale substrate into individual devices.
In an exemplary Dynamic Random Access Memory (DRAM) manufacturing process, a finished wafer including a plurality of die locations thereon is singulated (diced) into individual component parts, each part comprising a single semiconductor die. Each semiconductor die is then placed into, for example, a small outline j-lead package (SOJ), a tape-automated small outline package (TSOP) or processed with minimal additional components into a die scale package (CSP). Once assembly of the individual packaged dice is completed, they are taken through preburn-in test, burn-in and final low- and high-speed testing.
In an effort to streamline back-end processes, many efforts have been focused on producing known good die (KGD) through implementation of test methods utilizing wafer probes. Such tests include voltage screens, usage of integrated circuit quiescent current (Iddq) and temperature tests performed at the wafer level. Currently, the industry relies heavily on test carriers to burn-in and test singulated (diced) semiconductor dice to obtain a quality level for KGDs which consumers of the semiconductor dice desire and expect. However, test carrier methods are expensive, relatively slow and, in many cases, cost prohibitive.
One reason that more tests are not performed at the wafer level is that many of such tests require a large number of simultaneous, precise connections with each of the various dice locations on the wafer. In addition, a large number of power and signal input/output (I/O) paths between the dice locations on the wafer and test circuitry are required. For example, a wafer includes several hundred to well over a thousand semiconductor dice fabricated thereon, with each individual semiconductor die having numerous bond pads or contact locations. The total number of bond pads on the wafer is generally in the thousands. For some testing procedures, an I/O path must be provided to each bond pad on the die. Even with wafer stepping techniques, probe cards utilized in such testing usually do not include enough probes or contact bumps to effectively test groups of semiconductor dice on a wafer, each semiconductor die having a large number of contact locations. As integrated circuits become faster and ever-more complex, the number of I/O paths increases drastically, further exacerbating testing problems.
Since integrated circuitry density increases with die complexity, often in conjunction with static or even reduced die size, as the number of I/O paths increases the bond pads used to provide such contacts are reduced in size and pitch (spacing), making it more difficult to achieve dependable contacts using conventional test probe cards for die-sort testing. Traditionally, bond pads were placed at either the die periphery or along a center line thereof but, as the number of required bond pads increases, an array format for bond pads has become more common, such bond pad arrays further complicating probe card design.
Another significant problem in semiconductor device production exists in being able to quickly and reliably test and burn-in dice at an early stage of production without damaging bond pads located on the active surface of the die or the underlying electrical traces. This problem is demonstrated in the use of probe cards representative of the current state of the art.
Probe cards are conventionally used to contact the electrical pads of a wafer or one or more of the semiconductor dice located thereon, establish temporary electrical connection and perform one or more tests on the wafer or semiconductor dice through associated external circuitry. Often this is accomplished by contacting the bond pads of a semiconductor die, performing the test and then stepping the probe card to another semiconductor die on the wafer. In making electrical contact with the wafer surface, the probe card often performs a scrubbing action which allows for the electrical probes on the probe card to penetrate a thin metal oxide layer formed on the bond pads. In performing such a scrubbing action the probes, often in the form of a needle probe, may become displaced such that alignment of the probe tips, both vertically and laterally, becomes less and less accurate with time and use.
Additionally, in performing this aforementioned scrubbing action, a probe card may be overdriven, meaning that once contact is made between a probe and a bond pad on the wafer, the probe is pressed even further into the wafer in order to deflect the probes laterally across the contact pad to scrape the oxide layer. As transistor density increases, the size of each bond pad typically decreases along with the pitch or spacing between the bond pads and the metal thickness of the bond pad itself. Smaller bond pads result in a higher likelihood of piercing through the metal surface of the bond pad with a probe tip during scrubbing, or possibly collapsing the bond pad and/or any underlying electrical trace. Decreased bond pad pitch or spacing also means that less lateral movement by the probe for a scrubbing action will be allowed.
In an effort to deal with such issues, the industry has pursued various alternative techniques. One technique used to deal with probe alignment issues is the use of membrane type probe cards. Membrane probe cards are typically formed of a thin and flexible dielectric material such as polyimide. Contact bumps are formed on the membrane in electrical communication with conductive traces carried by the card. The conductive traces are electrically connected to external test circuitry which implements, controls and records the testing.
In general, membrane probes are able to compensate for vertical misalignment between the contact locations on the wafer. In effecting such alignment, membrane probes typically utilize a force applying mechanism which allows the contact bumps to penetrate the oxide layer on the bond pads. Membrane probes typically substitute this penetrating action for the scrubbing technique used with needle-type probes in order to penetrate the oxidation layer of a die's bond pads.
One disadvantage of such membrane probes is that vertical overdrive forces are required to achieve penetration of the probe through the oxide layer and associated electrical contact. Such vertical forces can damage the bond pads on the wafer and possibly the underlying traces. As noted above, with increased density of electrical I/O contacts in the form of bond pads, and the inherent reduction of their size and spacing, the likelihood of damage to the bond pads is also increased.
Another disadvantage of membrane probe cards is the disparate rate of thermal expansion between elements of the probe card and a wafer. For example, due to disparate coefficient of thermal expansion (CTE), copper traces on the probe card will expand and contract at a significantly different rate than the semiconductor material of the wafer as a result of temperature fluctuations during testing. The mismatch of thermal properties may cause alignment problems between a probe card and semiconductor die, particularly during high temperature testing such as is conducted during burn-in.
Additionally, traditional methods of utilizing probe cards for interfacing a wafer or semiconductor die location thereon with a tester introduce parasitic capacitance and stray inductance, each of which prevents a die under test from being tested at its design speed. This deficiency allows for testing and qualification of semiconductor dice as functional, but which fail, undetected, to meet speed requirements. Thus, such semiconductor dice are further processed and packaged, only to be scrapped at a later time when the operational speed deficiency is discovered. Such problems resulting from ineffective test procedures will only be exacerbated in the future as semiconductor devices continue to increase in speed as well as in density of transistors for a given semiconductor die. Because scrapping or reworking finished (packaged) dice that do not meet speed requirements is prohibitively expensive, it will be desirable to test multi-chip modules such as memory modules at normal operational speed and then replace the speed-deficient dice which may have otherwise tested as functional. To further complicate problems, the output drivers of the semiconductor dice will be downsized in anticipation of reduced parasitics between dice, with an attendant reduction in effectiveness in driving the probe card and tester. Thus, accurate sorting of semiconductor dice at the wafer level would save significant packaging cost.
In view of the shortcomings in the art, it would be advantageous to provide a full-wafer probe card affording higher speeds and higher resolution, and which is suitable for high-temperature burn-in testing on a wafer scale, prior to die singulation and packaging. In addition, it would be desirable to employ probe cards which place less of a load on the output drivers of a device under test. It would also be advantageous to provide a probe card which may be fabricated in commercial quantities with processes which are well known and utilized in the formation of integrated circuits. Further, it would be advantageous to provide a probe card which minimizes stray capacitance and inductance allowing for high frequency testing under real operating conditions.